1. Field of the Invention
The present invention relates to a leadless chip carrier having terminals to be connected to external circuits (hereinafter referred to as "electrode terminals") on the bottom thereof in place of lead wires and a process for the fabrication of the same. More particularly, the present invention relates to an improvement on the construction of such electrode terminals.
2. Description of the Prior Art
Recently, with increase of demand for reducing size and weight and further for enhancing performance of electronic equipments, leadless chip carriers having electrode terminals become utilized in IC (integrated circuits) or elements such as diode which compose circuits in place of discrete type connecting means having lead wires.
FIGS. 1(a) and 1(b) show an example of conventional leadless chip carriers which are now widely used wherein FIG. 1(a) is a bottom plan view showing a leadless chip carrier 10, and FIG. 1(b) is a side view of the leadless chip carrier 10 in FIG. 1(a).
The leadless chip carrier 10 comprises an insulation layer 11, electrode terminals 12, and a cap 13 for protecting internal circuit.
In mounting such leadless chip carrier 10 on a printed circuit board (not shown), there have been typically two conventional methods which will be described hereinbelow.
One is a so-called reflowing method wherein creamlike soldering paste has previously been applied on the surface of the electric circuit pattern on a printed circuit board to which the leadless chip carrier 10 is to connect, the bottom of the leadless chip carrier 10 is temporarily fixed by utilizing adhesiveness of the soldering paste, and then the soldering paste is heated at an elevated temperature to remelt the same for bonding.
According to the reflowing method, there is such an advantage that a favourable soldering can be effected irrespective of a construction of the electrode terminals 12, besides an area of the soldered joint is very small so that high density assembly of a device becomes possible. On the other hand, there is such a disadvantage that a position of the leadless chip carrier 10 is easily deviated because of flowability of solder when the soldering paste is remelted at the elevated temperature. Particularly, when a chip carrier having a narrow lead spacing are attached to a printed-circuit board, adjacent leads are likely to be short-circuited, even if the aforesaid deviation is very slight, and as a result, it is difficult to attain high density assembly. In addition, since a surface of metallized layer of the electrode terminal 12 is flat as shown in FIG. 1(b), a sufficient amount of solder cannot be applied to a portion where the metallized layer contacts with a conductor of the printed circuit board, and hence, sufficient bonding strength could not be attained.
Another method has been proposed to solve the above-mentioned problems wherein first, the bottom of the leadless chip carrier 10 is bonded to a desired position of the printed circuit board by the use of a bonding material, and then the leadless chip carrier 10 is immersed in a bath of molten solder together with the printed circuit board. In accordance with this method, bonding strength is undoubtedly elevated as compared with that of the former method. However, this method is likely to cause soldering failure or imperfect soldering due to solder bridge or collected flux produced in its soldering process in the case where a plurality of the leadless chip carriers 10 are mounted closely to each other. Thus, considerable time and man-power are often required for correcting the troubled portions after completing the soldering.
Accordingly, it is an object of the present invention to provide a leadless chip carrier by which strength and reliability bonding of the leadless chip carrier to conductors on a printed circuit board can be elevated, so that high-density assembly becomes possible.